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FPGA / RTL

8-bit RISC-V Processor

RV32I instruction set table
SystemVerilog RISC-V ISA Basys3 FPGA RTL Design Vivado Testbench

A RISC-V instruction decoder implemented in SystemVerilog and synthesized on a Basys3 FPGA. Decodes all major instruction formats — R, I, S, B, U, and J-type — extracting register fields, immediates, and control signals from a 32-bit instruction word. Includes a complete testbench verifying ADD, ADDI, LW, SW, BEQ, LUI, and JAL.

datapath diagram

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instr[31:0] Decoder riscv_decoder instr[6:0] opcode instr[11:7] rd instr[14:12] funct3 instr[19:15] rs1 instr[24:20] rs2 instr[31:25] funct7 rd [4:0] rs1 [4:0] rs2 [4:0] funct3 [2:0] funct7 [6:0] imm [31:0] Register File x0–x31 rd → write addr rs1 → read port A rs2 → read port B Imm Gen sign-extend R/I/S/B/U/J → 32-bit imm Control reg_write mem_read mem_write branch alu_src control signals ALU op: funct3 / funct7 src: rs2 or imm out: result, zero imm (alu_src mux) R · I · I(load) · S · B · U(LUI) · U(AUIPC) · J(JAL) · I(JALR)

overview

The decoder is the first stage of a single-cycle RISC-V pipeline. It takes a 32-bit instruction and extracts all fields needed by downstream stages: register addresses, the immediate value, and five control signals that drive the register file, ALU, and memory.

All logic is purely combinational — no clock, no state. The opcode in instr[6:0] selects which instruction format to interpret, and each format scatters its immediate across different bit fields of the instruction word.

instruction formats

TypeOpcodeInstructionsImmediate encodingControl
R0110011ADD, SUB, AND, OR, XORnone (imm = 0)reg_write, alu_src=0
I0010011ADDI, ANDI, ORIsign-extend instr[31:20]reg_write, alu_src=1
I (load)0000011LW, LB, LHsign-extend instr[31:20]reg_write, mem_read, alu_src=1
S0100011SW, SB, SH{instr[31:25], instr[11:7]}mem_write, alu_src=1
B1100011BEQ, BNE, BLTscrambled across [31,7,30:25,11:8]branch, alu_src=0
U (LUI)0110111LUI{instr[31:12], 12'b0}reg_write, alu_src=1
U (AUIPC)0010111AUIPC{instr[31:12], 12'b0}reg_write, alu_src=1
J1101111JALscrambled across [31,19:12,20,30:21]reg_write, alu_src=1
I (JALR)1100111JALRsign-extend instr[31:20]reg_write, alu_src=1

testbench

The decoder_tb module applies seven test vectors covering all major instruction formats. Each test drives a 32-bit instruction encoding, waits 10 time units for combinational propagation, then calls a check() task that compares all nine outputs against expected values and prints PASS or FAIL with a full diff on failure.

TestInstructionEncodingKey check
R-typeADD x3, x1, x20x0020_81B3reg_write=1, alu_src=0, imm=0
I-typeADDI x1, x1, 40x0040_8093reg_write=1, alu_src=1, imm=4
I-loadLW x2, 8(x1)0x0080_A103mem_read=1, alu_src=1, imm=8
S-typeSW x2, 8(x1)0x0020_A423mem_write=1, reg_write=0, imm=8
B-typeBEQ x1, x2, 160x0020_8863branch=1, alu_src=0, imm=16
U-typeLUI x5, 0x123450x1234_52B7reg_write=1, imm=0x12345000
J-typeJAL x1, 320x0200_00EFreg_write=1, alu_src=1, imm=32